In the electronics industry, the tendency has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of multiple interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards.
This increased integrated circuit density has led to the development of multi-chip packages, a package in package (PIP), a package on package (POP), or a combination thereof in which more than one integrated circuit can be packaged. Each package provides mechanical support for the individual integrated circuits and one or more layers of interconnect lines that enable the integrated circuits to be connected electrically to surrounding circuitry.
Typically, the packages on which the integrated semiconductor chips are mounted include a substrate or other chip-mounting device. Substrates are parts that provide a package with mechanical base support and a form of electrical interface that would allow the external world to access the devices housed within the package.
Current multi-chip packages, also commonly referred to as multi-chip modules, typically consist of a substrate onto which a set of separate integrated circuit components are attached. Such multi-chip packages have been found to increase integrated circuit density and miniaturization, improve signal propagation speed, reduce overall integrated circuit size and weight, improve performance, and lower costs all of which are primary goals and the modern trend of the integrate circuit industry.
Unfortunately, package warpage is a critical problem in multi-chip and multi-package packaging as well as single die packaging for large body sizes. In particular, for Package-on-Package (PoP) technology where typical flip chip interconnection is employed to interconnect the semiconductor chip to the base package, warpage of the base package has become a significant limitation making it unfeasible to meet typical warpage specifications for such packages.
In a typical flip chip package, a negative curvature (“crying” warpage) results after the chip attach and the underfill processes are completed. This is expected due to the coefficient of thermal expansion (CTE) mismatch between semiconductor chip and the substrate. The goal of the warpage control is to have the combination of the chip and the substrate as flat as possible. Since absolute flatness is impossible to achieve, typically, strict warpage specification is imposed. The curvature described above makes it difficult to meet the warpage specifications, particularly in case of 3-dimension (3D) packages like PoPb (PoP base package) for which the specifications are unusually stringent.
Thus, a need still remains for accommodating the modern trend of semiconductor manufacturing and packaging, achieving better control the package warpage, and increasing the packaging density. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.